1. Field of the Invention
Embodiments of the invention relate to a layout for a semiconductor memory device. More particularly, embodiments of the invention relate to a layout for distributed sense amplifier drivers adapted for use in a semiconductor memory device.
This application claims priority to Korean Patent Application No. 10-2005-0064756 filed on Jul. 18, 2005, the subject matter of which is incorporated by reference in its entirety.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a conventional bit line sense amplifier 100 and drivers 110 and 120. Referring to FIG. 1, bit line sense amplifier 100 is connected to a bit line BL and a complementary bit line BLB which are in turn connected to memory cells (not shown). Bit line sense amplifier 100 includes NMOS transistors 101 and 102 which are connected in series between the bit line BL and the complementary bit line BLB. The gate and drain of NMOS transistor 101 are respectively connected to the bit lines BLB and BL, and the gate and drain of NMOS transistor 102 are respectively connected to the bit lines BL and BLB. The sources of NMOS transistors 101 and 102 are connected to a ground voltage driver 110. Ground voltage driver 110 is an NMOS transistor having a gate connected to a first driving signal LAN and a source connected to a ground voltage VSS.
Bit line sense amplifier 100 further includes PMOS transistors 104 and 105 which are connected in series between the bit line BL and the complementary bit line BLB. The gate and drain of PMOS transistor 104 are respectively connected to the bit lines BLB and BL, and the gate and drain of PMOS transistor 105 are respectively connected to the bit lines BL and BLB. The sources of PMOS transistors 104 and 105 are connected to a supply voltage driver 120. Supply voltage driver 120 is a PMOS transistor having a gate connected to a second driving signal LAP and a source connected to a supply voltage VDD.
Bit line sense amplifier 100 and respective drivers 110 and 120 may be arranged in a semiconductor memory device, such as a dynamic random access memory (DRAM), as illustrated in the layout diagrams of FIGS. 2, 3, or 4.
Referring to FIG. 2, each one of a plurality of memory cell array blocks MCA includes a plurality of memory cells arranged in a matrix, a plurality of sense amplifier blocks SA respectively connected to bit lines associated with the memory cell array blocks MCA, and a plurality of word line driving blocks SWD respectively connected to word lines associated with the memory cell array blocks MCA. In addition, a conjunction block CONJ is located between respective sense amplifier blocks SA and associated word line driving blocks SWD.
Each sense amplifier block SA includes a plurality of the bit line sense amplifiers 100, like one illustrated in FIG. 1. In each conjunction block CONJ, sense amplifier drivers, (e.g., supply voltage driver 120 and ground voltage driver 110 of FIG. 1) are arranged in an alternating manner. An N-well region is formed to pass through the conjunction blocks CONJ having supply voltage driver 120, and through the sense amplifier blocks SA having PMOS transistors 104 and 105 of bit line sense amplifier 100.
Referring to FIG. 3, ground voltage driver 110, which is included in every other conjunction block CONJ in FIG. 2, is instead included in each sense amplifier block SA. That is, ground voltage driver 110 is divided into several constituent parts and arranged in each sense amplifier block SA, to thereby increase the driving efficiency of each bit line sense amplifier 100.
Referring to FIG. 4, supply voltage driver 120, which was included in each conjunction block CONJ in FIG. 3, is instead included together with ground voltage driver 110 in each sense amplifier block SA. Each supply voltage driver 120 and ground voltage driver 110 is divided into several constituent parts and arranged in the sense amplifier block SA, to thereby increase driving efficiency of each bit line sense amplifier 100.
However, when both supply voltage driver 120 and ground voltage driver 110 are included in a sense amplifier block SA, it is difficult to conform to the tolerances established by contemporary manufacturing design rules. More particularly, it is very difficult to maintain defined margins between an N-well region for the PMOS transistor of supply voltage driver 120 and an N-active region for the NMOS transistor of ground voltage driver 110. As a result, it is difficult to manufacture the desired sense amplifier block SA illustrated in FIG. 4, for example. In order to obtain this desired sense amplifier block SA it must be expanded in its constituent area in order to obtain the necessary manufacturing margin. This expansion causes an undesirable increase in the overall chip size.
Accordingly, there is a need for an arrangement of sense amplifier drivers having increased driving efficiencies that provides a required manufacturing margin without increasing the overall chip size.